Overview

This page outlines the Freescale i.MX53 features available as part of the Opal CPU Module.
It includes features that are available via external pins on the Opal, and does not detail internal functions such as memory controllers, internal timers etc.
Please note also that not all features listed may be supported by your chosen operating system.
Each section includes:

A brief overview of the feature along with any specific Opal implementation notes
List of external signals used with the interface. These signals are likely to be multiplexed with other signals. The following chapter details each external signal on the Opal CPU module along with i.MX53 functions available on each pad.

This page does not include in-depth information on each feature. Please refer to the appropriate section of the Freescale i.MX53 manual for this information.

Display Controller

The i.MX53 includes 5 display interfaces:

2x LVDS
2x parallel RGB
Analog VGA

Two of these interfaces may be used at the same time to drive independent displays. A combined rate of up to 180 MP/sec is supported. This means a single 1080p (1920x1080) display, or two displays of lower frequency.

While the silicon supports dual, independent displays, we do not currently have software support for this feature. Contact us if this is important for your application.

Pin	Signal Name	Voltage	Primary Pin Name
VGA
B-39	TVDAC_IOR	Analog	TVDAC_IOR
B-40	TVDAC_IOG	Analog	TVDAC_IOG
B-42	TVDAC_IOB	Analog	TVDAC_IOB
B-41	TVDAC_IOR_BACK	Analog	TVDAC_IOR_BACK
B-38	TVDAC_IOG_BACK	Analog	TVDAC_IOG_BACK
B-43	TVDAC_IOB_BACK	Analog	TVDAC_IOB_BACK
DISP0 (Parallel RGB)
A-55	DISP0_DAT0	2.775V	DISP0_DAT0
A-56	DISP0_DAT1	2.775V	DISP0_DAT1
A-66	DISP0_DAT2	2.775V	DISP0_DAT2
A-70	DISP0_DAT3	2.775V	DISP0_DAT3
A-67	DISP0_DAT4	2.775V	DISP0_DAT4
A-57	DISP0_DAT5	2.775V	DISP0_DAT5
A-68	DISP0_DAT6	2.775V	DISP0_DAT6
A-49	DISP0_DAT7	2.775V	DISP0_DAT7
A-52	DISP0_DAT8	2.775V	DISP0_DAT8
A-72	DISP0_DAT9	2.775V	DISP0_DAT9
A-59	DISP0_DAT10	2.775V	DISP0_DAT10
A-50	DISP0_DAT11	2.775V	DISP0_DAT11
A-48	DISP0_DAT12	2.775V	DISP0_DAT12
A-71	DISP0_DAT13	2.775V	DISP0_DAT13
A-69	DISP0_DAT14	2.775V	DISP0_DAT14
A-61	DISP0_DAT15	2.775V	DISP0_DAT15
A-73	DISP0_DAT16	2.775V	DISP0_DAT16
A-51	DISP0_DAT17	2.775V	DISP0_DAT17
A-60	DISP0_DAT18	2.775V	DISP0_DAT18
A-62	DISP0_DAT19	2.775V	DISP0_DAT19
A-64	DISP0_DAT20	2.775V	DISP0_DAT20
A-75	DISP0_DAT21	2.775V	DISP0_DAT21
A-63	DISP0_DAT22	2.775V	DISP0_DAT22
A-54	DISP0_DAT23	2.775V	DISP0_DAT23
A-138	DI0_D0_CS	3.3V	EIM_D23
A-12	DIO_D1_CS	3.3V	EIM_A25
A-58	DI0_DISP_CLK	2.775V	DI0_DISP_CLK
A-135	DI0_PIN1	3.3V	EIM_D22
A-65	DI0_PIN2	2.775V	DI0_PIN2
A-76	DI0_PIN3	2.775V	DI0_PIN3
A-74	DI0_PIN4	2.775V	DI0_PIN4
A-125	DI0_PIN5	3.3V	EIM_D16
A-126	DI0_PIN6	3.3V	EIM_D17
A-134	DI0_PIN7	3.3V	EIM_D18
A-136	DI0_PIN8	3.3V	EIM_D19
A-131	DI0_PIN11	3.3V	EIM_D30
A-132	DI0_PIN12	3.3V	EIM_D31
A-140	DI0_PIN13	3.3V	EIM_D28
A-139	DI0_PIN14	3.3V	EIM_D29
A-53	DI0_PIN15	2.775V	DI0_PIN15
A-133	DI0_PIN16	3.3V	EIM_D20
A-128	DI0_PIN17	3.3V	EIM_D21
DISP1 (Parallel RGB)
B-47	DISP1_DAT0	3.3V	EIM_DA9
B-121	DISP1_DAT1	3.3V	EIM_DA8
B-111	DISP1_DAT2	3.3V	EIM_DA7
B-122	DISP1_DAT3	3.3V	EIM_DA6
B-112	DISP1_DAT4	3.3V	EIM_DA5
B-114	DISP1_DAT5	3.3V	EIM_DA4
B-123	DISP1_DAT6	3.3V	EIM_DA3
B-50	DISP1_DAT7	3.3V	EIM_DA2
B-113	DISP1_DAT8	3.3V	EIM_DA1
B-120	DISP1_DAT9	3.3V	EIM_DA0
B-118	DISP1_DAT10	3.3V	EIM_EB1
B-49	DISP1_DAT11	3.3V	EIM_EB0
A-157	DISP1_DAT12	3.3V	EIM_A17
A-153	DISP1_DAT13	3.3V	EIM_A18
A-16	DISP1_DAT14	3.3V	EIM_A19
A-156	DISP1_DAT15	3.3V	EIM_A20
A-15	DISP1_DAT16	3.3V	EIM_A21
A-14	DISP1_DAT17	3.3V	EIM_A22
A-13	DISP1_DAT18	3.3V	EIM_A23
A-154	DISP1_DAT19	3.3V	EIM_A24
A-132	DISP1_DAT20	3.3V	EIM_D31
A-131	DISP1_DAT21	3.3V	EIM_D30
A-127	DISP1_DAT22	3.3V	EIM_D26
A-129	DISP1_DAT23	3.3V	EIM_D27
B-117 A-134	DI1_D0_CS	3.3V 3.3V	EIM_DA13 EIM_D18
B-60	DI1_D1_CS	3.3V	EIM_DA14
A-155	DI1_DISP_CLK	3.3V	EIM_A16
B-46	DI1_PIN1	3.3V	EIM_DA15
B-116 A-138	DI1_PIN2	3.3V 3.3V	EIM_DA11 EIM_D23
B-51 B-59	DI1_PIN3	3.3V 3.3V	EIM_DA12 EIM_EB3
B-46	DI1_PIN4	3.3V	EIM_DA15
B-57	DI1_PIN5	3.3V	EIM_CS0
B-56	DI1_PIN6	3.3V	EIM_CS1
B-55	DI1_PIN7	3.3V	EIM_OE
B-45	DI1_PIN8	3.3V	EIM_RW
A-127	DI1_PIN11	3.3V	EIM_D26
A-12	DI1_PIN12	3.3V	EIM_A25
A-129	DI1_PIN13	3.3V	EIM_D27
A-138	DI1_PIN14	3.3V	EIM_D23
B-115 A-139	DI1_PIN15	3.3V 3.3V	EIM_DA10 EIM_D29
B-59	DI1_PIN16	3.3V	EIM_EB3
B-119	DI1_PIN17	3.3V	EIM_LBA
LVDS0
A-151	LVDS0_TX0_P		LVDS0_TX0_P
A-150	LVDS0_TX0_N		LVDS0_TX0_N
A-148	LVDS0_TX1_P		LVDS0_TX1_P
A-149	LVDS0_TX1_N		LVDS0_TX1_N
A-143	LVDS0_TX2_P		LVDS0_TX2_P
A-142	LVDS0_TX2_N		LVDS0_TX2_N
A-145	LVDS0_TX3_P		LVDS0_TX3_P
A-144	LVDS0_TX3_N		LVDS0_TX3_N
A-146	LVDS0_CLK_P		LVDS0_CLK_P
A-147	LVDS0_CLK_N		LVDS0_CLK_N
LVDS1
A-19	LVDS1_TX0_P		LVDS1_TX0_P
A-18	LVDS1_TX0_N		LVDS1_TX0_N
A-21	LVDS1_TX1_P		LVDS1_TX1_P
A-20	LVDS1_TX1_N		LVDS1_TX1_N
A-25	LVDS1_TX2_P		LVDS1_TX2_P
A-24	LVDS1_TX2_N		LVDS1_TX2_N
A-27	LVDS1_TX3_P		LVDS1_TX3_P
A-26	LVDS1_TX3_N		LVDS1_TX3_N
A-23	LVDS1_CLK_P		LVDS1_CLK_P
A-22	LVDS1_CLK_N		LVDS1_CLK_N

Camera Ports (CSI)

The i.MX53 has two camera ports - each controlled by a CSI sub-block, providing a connection to image sensors and related devices. These ports are part of the IPU block. Not all signals are available on the Opal interface for CSI0.

Pin	Signal Name	Voltage	Primary Pin Name	Notes
CSI0
A-129	CSI0_D0	3.3V	EIM_D27
A-127	CSI0_D1	3.3V	EIM_D26
A-132	CSI0_D2	3.3V	EIM_D31
A-131	CSI0_D3	3.3V	EIM_D30
A-44	CSI0_D4	1.8V	CSI0_DAT4
A-43	CSI0_D5	1.8V	CSI0_DAT5
A-30	CSI0_D6	1.8V	CSI0_DAT6
A-39	CSI0_D7	1.8V	CSI0_DAT7
	CSI0_D8			Not available on Opal interface (dedicated to I2C1)
	CSI0_D9
A-40	CSI0_D10	1.8V	CSI0_DAT10
A-42	CSI0_D11	1.8V	CSI0_DAT11
A-36	CSI0_D12	1.8V	CSI0_DAT12
A-29	CSI0_D13	1.8V	CSI0_DAT13
A-41	CSI0_D14	1.8V	CSI0_DAT14
A-38	CSI0_D15	1.8V	CSI0_DAT15
A-37	CSI0_D16	1.8V	CSI0_DAT16
A-32	CSI0_D17	1.8V	CSI0_DAT17
A-35	CSI0_D18	1.8V	CSI0_DAT18
A-31	CSI0_D19	1.8V	CSI0_DAT19
A-33	CSI0_DATA_EN	1.8V	CSI0_DATA_EN
A-45	CSI0_HSYNC	1.8V	CSI0_MCLK
A-34	CSI0_VSYNC	1.8V	CSI0_VSYNC
A-46	CSI0_PIXCLK	1.8V	CSI0_PIXCLK
CSI1
B-47	CSI1_D0	3.3V	EIM_DA9
B-121	CSI1_D1	3.3V	EIM_DA8
B-111	CSI1_D2	3.3V	EIM_DA7
B-122	CSI1_D3	3.3V	EIM_DA6
B-112	CSI1_D4	3.3V	EIM_DA5
B-114	CSI1_D5	3.3V	EIM_DA4
B-123	CSI1_D6	3.3V	EIM_DA3
B-50	CSI1_D7	3.3V	EIM_DA2
B-113	CSI1_D8	3.3V	EIM_DA1
B-120	CSI1_D9	3.3V	EIM_DA0
B-118	CSI1_D10	3.3V	EIM_EB1
B-49	CSI1_D11	3.3V	EIM_EB0
A-157	CSI1_D12	3.3V	EIM_A17
A-153	CSI1_D13	3.3V	EIM_A18
A-16	CSI1_D14	3.3V	EIM_A19
A-156	CSI1_D15	3.3V	EIM_A20
A-15	CSI1_D16	3.3V	EIM_A21
A-14	CSI1_D17	3.3V	EIM_A22
A-13	CSI1_D18	3.3V	EIM_A23
A-154	CSI1_D19	3.3V	EIM_A24
B-115 A-138	CSI1_DATA_EN	3.3V 3.3V	EIM_DA10 EIM_D23
B-116 B-59	CSI1_HSYNC	3.3V 3.3V	EIM_DA11 EIM_EB3
A-155	CSI1_PIXCLK	3.3V	EIM_A16
B-51 A-139	CSI1_VSYNC	3.3V 3.3V	EIM_DA12 EIM_D29

Audio (AUDMUX)

The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect device for voice, audio, and synchronous data routing between host serial interfaces such as the Synchronous Serial Interface Controller (SSI) and peripheral serial interfaces (audio and voice codecs).
Key features include:

Full 6-wire SSI interfaces for asynchronous receive and transmit
Configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interfaces
Independent Tx/Rx Frame sync and clock direction selection for host or peripheral
Each host interface's capability to connect to any other host or peripheral interface in a point-to-point or point-to-multipoint (network mode)
Transmit and Receive Data switching to support external network mode

Pin	Signal Name	Voltage	Primary Pin Name
AUD3
A-40	AUD3_RXC	1.8V	CSI0_DAT10
A-39	AUD3_RXD	1.8V	CSI0_DAT7
A-42	AUD3_RXFS	1.8V	CSI0_DAT11
A-44	AUD3_TXC	1.8V	CSI0_DAT4
A-43	AUD3_TXD	1.8V	CSI0_DAT5
A-30	AUD3_TXFS	1.8V	CSI0_DAT6
AUD4
A-62 B-97	AUD4_RXC	2.775V 3.3V	DISP0_DAT19 SD2_CMD
A-54 B-100	AUD4_RXD	2.775V 3.3V	DISP0_DAT23 SD2_DATA0
A-60 B-101	AUD4_RXFS	2.775V 3.3V	DISP0_DAT18 SD2_CLK
A-64 B-102	AUD4_TXC	2.775V 3.3V	DISP0_DAT20 SD2_DATA3
A-75 B-99	AUD4_TXD	2.775V 3.3V	DISP0_DAT21 SD2_DATA2
A-63 B-98	AUD4_TXFS	2.775V 3.3V	DISP0_DAT22 SD2_DATA1
AUD5
A-69 A-130	AUD5_RXC	2.775V 3.3V	DISP0_DAT14 EIM_D25
A-62 B-87	AUD5_RXD	2.775V 3.3V	DISP0_DAT19 KEY_ROW1
A-71 A-137	AUD5_RXFS	2.775V 3.3V	DISP0_DAT13 EIM_D24
A-73 B-90	AUD5_TXC	2.775V 3.3V	DISP0_DAT16 KEY_COL0
A-51 B-94	AUD5_TXD	2.775V 3.3V	DISP0_DAT17 KEY_ROW0
A-60 B-89	AUD5_TXFS	2.775V 3.3V	DISP0_DAT18 KEY_COL1
AUD6
A-74	AUD6_RXD	2.775V	DIO_PIN4
A-53	AUD6_TXC	2.775V	DIO_PIN15
A-65	AUD6_TXD	2.775V	DIO_PIN2
A-76	AUD6_TXFS	2.775V	DIO_PIN3

Enhanced Secure Digital (SD) Controllers

The i.MX53 has four 4 eSDHC controllers. These handle SD/SDIO and MMC protocols.
There are 2 different versions of the host controller present in the i.MX53 – v2 and v3 which adds support for version 4.4 MMC cards. Refer to the Freescale manual for more details on the differences. The v3 support is implemented on eSDHC3.

Pin	Signal Name	Voltage	Primary Pin Name	Notes
ESDHC1
B-105	ESDHC1_CLK	3.3V	ESDHC1_CLK
B-108	ESDHC1_CMD	3.3V	ESDHC1_CMD
B-104	ESDHC1_DAT0	3.3V	ESDHC1_DAT0
B-106	ESDHC1_DAT1	3.3V	ESDHC1_DAT1
B-109	ESDHC1_DAT2	3.3V	ESDHC1_DAT2
B-107	ESDHC1_DAT3	3.3V	ESDHC1_DAT3
A-118	ESDHC1_DAT4	3.3V	PATA_DATA8
A-119	ESDHC1_DAT5	3.3V	PATA_DATA9
A-120	ESDHC1_DAT6	3.3V	PATA_DATA10
A-110	ESDHC1_DAT7	3.3V	PATA_DATA11
A-87	ESDHC1_CD	3.3V	GPIO_1
A-96 A-74	ESDHC1_WP	3.3V 2.775V	GPIO_9 DIO_PIN4
A-99	ESDHC1_LCTL	3.3V	GPIO_18
ESDHC2
B-101	ESDHC2_CLK	3.3V	ESDHC2_CLK
B-97	ESDHC2_CMD	3.3V	ESDHC2_CMD
B-100	ESDHC2_DAT0	3.3V	ESDHC2_DAT0
B-98	ESDHC2_DAT1	3.3V	ESDHC2_DAT1
B-99	ESDHC2_DAT2	3.3V	ESDHC2_DAT2
B-102	ESDHC2_DAT3	3.3V	ESDHC2_DAT3
A-117	ESDHC2_DAT4	3.3V	PATA_DATA12
A-115	ESDHC2_DAT5	3.3V	PATA_DATA13
A-116	ESDHC2_DAT6	3.3V	PATA_DATA14
A-121	ESDHC2_DAT7	3.3V	PATA_DATA15
A-94	ESDHC2_CD	3.3V	GPIO_4
A-97	ESDHC2_WP	3.3V	GPIO_2
A-88	ESDHC2_LCTL	3.3V	GPIO_6
ESDHC3
A-114	ESDHC3_CLK	3.3V	PATA_IORDY
A-112	ESDHC3_CMD	3.3V	PATA_RESET_B
A-118	ESDHC3_DAT0	3.3V	PATA_DATA8
A-119	ESDHC3_DAT1	3.3V	PATA_DATA9
A-120	ESDHC3_DAT2	3.3V	PATA_DATA10
A-110	ESDHC3_DAT3	3.3V	PATA_DATA11
	ESDHC3_DAT4			Not available on the Opal module interface.
	ESDHC3_DAT5
	ESDHC3_DAT6
	ESDHC3_DAT7
A-101	ESDHC3_RST	3.3V	PATA_DA_0
ESDHC4
A-113	ESDHC1_CLK	3.3V	PATA_DA_2
A-105	ESDHC1_CMD	3.3V	PATA_DA_1
A-117	ESDHC1_DAT0	3.3V	PATA_DATA12
A-115	ESDHC1_DAT1	3.3V	PATA_DATA13
A-116	ESDHC1_DAT2	3.3V	PATA_DATA14
A-121	ESDHC1_DAT3	3.3V	PATA_DATA15
	ESDHC1_DAT4			Not available on the Opal module interface.
	ESDHC1_DAT5
	ESDHC1_DAT6
	ESDHC1_DAT7

SATA

The SATA feature has not been verified with any of our supported Operating Systems. Contact us if this feature is important for your project.

A SATA controller and PHY are included on the i.MX53 and exposed through the Opal interface.
The following features are supported:

Compliant with the following specifications:
Serial ATA 2.6
AHCI Revision 1.3 (except FIS-based switching)
AMBA 2.0 from ARM
SATA 1.5 Gb/s speed.
eSATA (external analog logic also needs to support eSATA)
RX data buffer for recovered clock systems
Data alignment circuitry when RX data buffer is also included
OOB signalling detection and generation
8b/10b encoding/decoding
Asynchronous signal recovery, including retry polling
Power management features including automatic partial-to-slumber transition
BIST loopback modes
Supports one SATA device(port0)
Configurable AMBA AHB interface (one master and one slave for each interface)
Internal DMA engine
Hardware-assisted Native Command Queuing for up to 32 entries
Port Multiplier with command-based switching
Disabling RX and TX Data clocks during power down modes

Pin	Signal Name	Voltage	Primar Pin Name
B-71	SATA_TXM	Analog	SATA_TXM
B-72	SATA_TXP	Analog	SATA_TXP
B-73	SATA_RXP	Analog	SATA_RXP
B-74	STAT_RXM	Analog	STAT_RXM

USB Host and On-The-Go Ports

Opal supports one USB Host controller and PHY, and one OTG controller and PHY. Both of these ports support USB 2.0 480Mbps operation.
The i.MX53 has two additional host controllers, however these ports require an external PHY and not all signals may be available.

Pin	Signal Name	Voltage	Primary Pin Name
USB OTG
B-76	USB_OTG_DP	Analog	USB_OTG_DP
B-77	USB_OTG_DM	Analog	USB_OTG_DM
B-81	USB_OTG_ID		USB_OTG_ID
B-82	USB_OTG_VBUS		USB_OTG_VBUS
USB HOST
B-78	USB_H1_DP	Analog	USB_H1_DP
B-79	USB_H1_DM	Analog	USB_H1_DM
B-83	USB_H1_VBUS		USB_H1_VBUS

Serial UART

The i.MX53 has 5 UARTS with the following features:

High-speed TIA/EIA-232-F compatible, up to 4.0 Mbit/s
Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
7 or 8 data bits
1 or 2 stop bits
Programmable parity (even, odd, and no parity)
Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
Edge-selectable RTS and edge-detect interrupts
Status flags for various flow control and FIFO states
Voting logic for improved noise immunity (16x oversampling)
Transmitter FIFO empty interrupt suppression
UART internal clocks enable/disable
Auto baud rate detection (up to 115.2 Kbit/s)
Receiver and transmitter enable/disable for power saving
DCE/DTE capability
RTS, IrDA asynchronous wake (AIRINT), receive asynchronous wake (AWAKE), RI (DTE only), DCD (DTE only), DTR (DCE only) and DSR (DTE only) interrupts wake the processor from STOP mode
Maskable interrupts
Two DMA Requests (TxFIFO DMA Request and RxFIFO DMA Request)
Escape character sequence detection
Software reset (SRST)
Two independent, 32-entry FIFOs for transmit and receive

Pin	Signal Name	Voltage	Primary Pin Name
UART1
A-42 A-107	UART1_RXD	1.8V 3.3V	CSI0_DAT11 PATA_DMACK
A-40 A-106	UART1_TXD	1.8V 3.3V	CSI0_DAT10 PATA_DIOW
A-114 A-133	UART1_RTS	3.3V 3.3V	PATA_IORDY EIM_D20
A-112 A-136	UART1_CTS	3.3V 3.3V	PATA_RESET_B EIM_D19
A-138	UART1_DCD	3.3V	EIM_D23
A-130	UART1_DSR	3.3V	EIM_D25
A-137	UART1_DTR	3.3V	EIM_D24
B-59	UART1_RI	3.3V	EIM_EB3
UART2
A-90 A-104 A-129	UART2_RXD	3.3V 3.3V 3.3V	GPIO_8 PATA_BUFFER_EN EIM_D27
A-92 A-108 A-127	UART2_TXD	3.3V 3.3V 3.3V	GPIO_7 PATA_DMARQ EIM_D26
A-109 A-139	UART2_RTS	3.3V 3.3V	PATA_DIOR EIM_D29
A-102 A-140	UART2_CTS	3.3V 3.3V	PATA_INTRQ EIM_D28
UART3
A-111 A-130	UART3_RXD	3.3V 3.3V	PATA_CS_1 EIM_D25
A-103 A-137	UART3_TXD	3.3V 3.3V	PATA_CS_0 EIM_D24
A-105 A-132 B-59	UART3_RTS	3.3V 3.3V 3.3V	PATA_DA_2 EIM_D31 EIM_EB3
A-113 A-131 A-138	UART3_CTS	3.3V 3.3V 3.3V	PATA_DA_1 EIM_D30 EIM_D23
UART4
A-29 B-94	UART4_RXD	1.8V 3.3V	CSI0_DAT13 KEY_ROW0
A-36 B-90	UART4_TXD	1.8V 3.3V	DSI0_DAT12 KEY_COL0
A-37	UART4_RTS	1.8V	CSI0_DAT16
A-32	UART4_CTS	1.8V	CSI0_DAT17
UART5
A-38 B-87	UART5_RXD	1.8V 3.3V	CSI0_DAT15 KEY_ROW1
A-41 B-89	UART5_TXD	1.8V 3.3V	CSI0_DAT14 KEY_COL1
A-35 B-93	UART5_RTS	1.8V 3.3V	CSI0_DAT18 KEY_COL4
A-31 B-86	UART5_CTS	1.8V 3.3V	CSI0_DAT19 KEY_ROW4

FlexCAN

The i.MX53 includes 2 FlexCAN controllers with these distinctive features:

Full Implementation of the CAN protocol specification
Standard data and remote frames
Extended data and remote frames
Zero to eight bytes data length
Programmable bit rate up to 1 Mb/sec
Content-related addressing
Flexible Message Buffers of zero to eight bytes data length
Each Message Buffer configurable as Rx or Tx, all supporting standard and extended messages
Individual Rx Mask Registers per Message Buffer
Includes 1056 bytes (64 Mbytes) of RAM used for Message Buffer storage
Includes 256 bytes (64 Mbytes) of RAM used for individual Rx Mask Registers
Full featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
Selectable backwards compatibility with previous CAN version
Programmable clock source to the CAN Protocol Interface, either bus clock or crystal oscillator
Unused message buffer and Rx Mask Register space can be used as general purpose RAM space
Listen only mode capability
Programmable loop-back mode supporting self-test operation
Programmable transmission priority scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
Short latency time due to an arbitration scheme for high-priority messages
Low power modes, with programmable wake up on bus activity
Configurable Glitch filter width to filter the noise on CAN bus when waking up

Pin	Signal Name	Voltage	Primary Pin Name
CAN1
A-90 B-91 A-109	CAN1_RXCAN	3.3V 3.3V 3.3V	GPIO_8 KEY_ROW2 PATA_DIOR
A-92 B-92 A-102	CAN1_TXCAN	3.3V 3.3V 3.3V	GPIO_7 KEY_COL2 PATA_INTRQ
CAN2
B-86 A-114	CAN2_RXCAN	3.3V 3.3V	KEY_ROW4 PATA_IORDY
B-93 A-112	CAN2_TXCAN	3.3V 3.3V	KEY_COL4 PATA_RESET_B

GPIO

The i.MX53 has seven 32-bit GPIO ports. GPIO pins are not multiplexed to more than one pin.
The Interface Signals section includes a column showing where each GPIO signal is available.
The GPIO includes the following features:

General purpose input/output logic capabilities:
Drives specific data to output using the data register (GPIO_DR)
Controls the direction of the signal using the GPIO direction register (GPIO_GDR)
Enables the core to sample the status of the corresponding inputs by reading the pad sample register (GPIO_PSR).
GPIO interrupt capabilities:
Supports up to 32 interrupts
Identifies interrupt edges
Generates three active-high interrupts to the i.MX53 interrupt controller

ECSPI and CSPI

The i.MX53 has 2 types of SPI ports:

Configurable SPI (one port)
Enhanced Configurable SPI (two ports)

The Configurable Serial Peripheral Interface (CSPI) controller provides full-duplex, synchronous, four-wire serial communication. It contains an 8 x 32 receive buffer (RXFIFO) and an 8 x 32 transmit buffer (TXFIFO).
The Enhanced Configurable Serial Peripheral Interface (ECSPI) contains a 64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer (TXFIFO).

Pin	Signal Name	Voltage	Primary Pin Name
CSPI
A-66 B-104 B-100 A-135	CSPI_MISO	2.775V 3.3V 3.3V 3.3V	DISP0_DAT2 SD1_DATA0 SD2_DATA0 EIM_D22
A-56 B-108 B-97 A-140	CSPI_MOSI	2.775V 3.3V 3.3V 3.3V	DISP0_DAT1 SD1_CMD SD2_CMD EIM_D28
A-49	CSPI_RDY	2.775V	DISP0_DAT7
A-55 B-105 B-101 A-128	CSPI_SCLK	2.775V 3.3V 3.3V 3.3V	DISP0_DAT0 SD1_CLK SD2_CLK EIM_D21
A-70 B-106 B-98 A-139 A-133	CSPI_SS0	2.775V 3.3V 3.3V 3.3V 3.3V	DISP0_DAT3 SD1_DATA1 SD2_DATA1 EIM_D29 EIM_D20
A-67 B-109 B-99 A-127	CSPI_SS1	2.775V 3.3V 3.3V 3.3V	DISP0_DAT4 SD1_DATA2 SD2_DATA2 EIM_A26
A-57 B-107 B-102 A-137	CSPI_SS2	2.775V 3.3V 3.3V 3.3V	DISP0_DAT5 SD1_DATA3 SD2_DATA3 EIM_D24
A-68 A-130	CSPI_SS3	2.775V 3.3V	DISP0_DAT6 EIM_D25
ECSPI1
A-30 A-63 B-89 A-126	ECSPI1_MISO	1.8V 2.775V 3.3V 3.3V	CSI0_DAT6 DISP0_DAT22 KEY_COL1 EIM_D17
A-43 A-75 B-94 A-134	ECSPI1_MOSI	1.8V 2.775V 3.3V 3.3V	CSI0_DAT5 DISP0_DAT21 KEY_ROW0 EIM_D18
A-93	ECSPI1_RDY	3.3V	GPIO_19
A-44 A-64 B-90 A-125	ECSPI1_SCLK	1.8V 2.775V 3.3V 3.3V	CSI0_DAT4 DISP0_DAT20 KEY_COL0 EIM_D16
A-39 A-54 B-87 B-58	ECSPI1_SS0	1.8V 2.775V 3.3V 3.3V	CSI0_DAT7 DISP0_DAT23 KEY_ROW1 EIM_EB2
A-61 B-92 A-136	ECSPI1_SS1	2.775V 3.3V 3.3V	DISP0_DAT15 KEY_COL2 EIM_D19
B-91 A-137	ECSPI1_SS2	3.3V 3.3V	KEY_ROW2 EIM_D24
B-88 A-130	ECSPI1_SS3	3.3V 3.3V	KEY_COL3 EIM_D25
ECSPI2
A-40 A-51 B-55	ECSPI2_MISO	1.8V 2.775V 3.3V	CSI0_DAT10 DISP0_DAT17 EIM_OE
A-73 B-56	ECSPI2_MOSI	2.775V 3.3V	DISP0_DAT16 EIM_CS1
A-12	ECSPI2_RDY	3.3V	EIM_A25
A-62 B-57	ECSPI2_SCLK	2.775V 3.3V	DISP0_DAT19 EIM_CS0
A-42 A-60 B-45	ECSPI2_SS0	1.8V 2.775V 3.3V	CSI0_DAT11 DISP0_DAT18 EIM_RW
A-61 B-119	ECSPI2_SS1	2.775V 3.3V	DISP0_DAT15 EIM_LBA
A-137	ECSPI2_SS2	3.3V	EIM_D24
A-130	ECSPI2_SS3	3.3V	EIM_D25

I2C

The i.MX53 has three I2C controllers. On Opal, two of these operate at 3.3V and one at 1.8V. I2C1 is used internally on Opal to communicate with the PMIC.
I2C controller features include:

Compatibility with I2C bus standard
Multiple-master operation
Software-programmable for one of 64 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection

Pin	Signal Name	Voltage	Primary Pin Name	Notes
I2C1
B-36	I2C1_SCL	1.8V	CSI0_DAT9	These pins are dedicated to I2C1. They are used as I2C1 internally on the Opal module to communicate to the PMIC.
B-35	I2C1_SDA	1.8V	CSI0_DAT8
I2C2
B-88 B-58	I2C2_SCL	3.3V 3.3V	KEY_COL3 EIM_EB2
B-95 A-125	I2C2_SDA	3.3V 3.3V	KEY_ROW3 EIM_D16
I2C3
A-89 A-86 A-126	I2C3_SCL	3.3V 3.3V 3.3V	GPIO_5 GPIO_3 EIM_D17
A-88 A-98 A-134	I2C3_SDA	3.3V 3.3V 3.3V	GPIO_6 GPIO_16 EIM_D18

Pulse Width Modulation (PWM)

The i.MX53 includes two PWM controllers. The Pulse Width Modulation (PWM) has a 16-bit counter, and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.

Pin	Signal Name	Voltage	Primary Pin Name
PWM1
A-96 A-52 B-107	PWM1_PWMO	3.3V 2.775V 3.3V	GPIO_9 DISP0_DAT8 SD1_DATA3
PWM2
A-87 A-72 B-109	PWM2_PWMO	3.3V 2.775V 3.3V	GPIO_1 DISP0_DAT9 SD1_DATA2

1-Wire Interface

The 1-Wire interface provides the communication link to a generic 1-Kbit add-only memory. It sends or receives one bit at a time with an option for software to manage the data using bytes. The required protocol for accessing the generic device is defined by Maxim-Dallas. The generic device holds battery characteristics information.

Pin	Signal Name	Voltage	Primary Pin Name	Notes
A-99 A-101	ONEWIRE_LINE	3.3V 3.3V	GPIO_18 PATA_DA_0

Keypad Port

The Keypad Port (KPP) can be used as a keypad matrix interface or as general purpose input/output (I/O). The KPP provides interface for the keypad matrix with 2-point contact or 3-point contact keys and is designed to simplify the software task of scanning a keypad matrix. With appropriate software support, the KPP is capable of detecting, de-bouncing, and decoding one or multiple keys pressed simultaneously on the keypad.
The KPP includes these features:

Supports up to an 8 x 8 external key pad matrix
Port pins can be used as general purpose I/O
Open drain design
Glitch suppression circuit design
Multiple-key detection
Long key-press detection
Standby key-press detection
Synchronizer chain clear
Supports a 2-point and 3-point contact key matrix

Pin	Signal Name	Voltage	Primary Pin Name
B-90	KPP_COL0	3.3V	KPP_COL0
B-89	KPP_COL1	3.3V	KPP_COL1
B-92	KPP_COL2	3.3V	KPP_COL2
B-88	KPP_COL3	3.3V	KPP_COL3
B-93	KPP_COL4	3.3V	KPP_COL4
A-95 A-44 A-93 B-101	KPP_COL5	3.3V 1.8V 3.3V 3.3V	GPIO_0 CSI0_DAT4 GPIO_19 SD2_CLK
A-96 A-30 B-102	KPP_COL6	3.3V 1.8V 3.3V	GPIO_9 CSI0_DAT6 SD2_DAT3
A-94 B-98	KPP_COL7	3.3V 3.3V	GPIO_4 SD2_DATA1
B-94	KPP_ROW0	3.3V	KPP_ROW0
B-87	KPP_ROW1	3.3V	KPP_ROW1
B-91	KPP_ROW2	3.3V	KPP_ROW2
B-95	KPP_ROW3	3.3V	KPP_ROW3
B-86	KPP_ROW4	3.3V	KPP_ROW4
A-87 A-43 B-97	KPP_ROW5	3.3V 1.8V 3.3V	GPIO_1 CSI0_DAT5 SD2_CMD
A-97 A-39 B-99	KPP_ROW6	3.3V 1.8V 3.3V	GPIO_2 CSI0_DAT7 SD2_DAT2
A-89 B-100	KPP_ROW7	3.3V 3.3V	GPIO_5 SD2_DAT0

System JTAG Controller

The System JTAG Controller (SJC) provides debug and test control with the maximum security. The test access port (TAP) is designed to support features compatible with the IEEE Standard 1149.1 v2001 (JTAG).
Refer to the Freescale documentation for details on setting up debug hardware to work with the i.MX53 via JTAG.

Pin	Signal Name	Voltage	Primary Pin Name	Notes
B-62	nTRST	1.8V	JTAG_nTRST
B-63	nSRST	1.8V	RESET_IN_B	Connected to RESET_IN_B on the i.MX53
B-64	TDO	1.8V	JTAG_TDO
B-65	TDI	1.8V	JTAG_TDI
B-66	TMS	1.8V	JTAG_TMS
B-67	TCK	1.8V	JTAG_TCK

Watchdog

The i.MX53 includes two watchdog timer blocks which have the following features:

A configurable time-out counter with Time-out periods from 0.5 seconds up to 128 seconds and after time-out expiration results in assertion of wdog_rst reset signal
Time resolution of 0.5 seconds
Configurable time-out counter that can be programmed to run or stop during low power modes
Configurable time-out counter that can be programmed to run or stop during DEBUG mode
Programmable Interrupt generation prior to time-out
The time duration between interrupt and time-out events can be programmed from 0 to 127.5 seconds in steps of 0.5 seconds
A power down counter with fixed time-out period of 16 seconds which if not disabled after reset will assert WDOG-1 signal low
Power down counter will be enabled out of any reset (POR, Warm / Cold reset) by default

Pin	Signal Name	Voltage	Primary Pin Name
WDOG1
A-96 A-52 B-109	WDOG_B	3.3V 2.775V 3.3V	GPIO_9 DISP0_DAT8 SD1_DATA2
B-109	WDOG_RST_B_DEB	3.3V	SD1_DATA2
WDOG2
A-87 A-72 B-107	WDOG_B	3.3V 2.775V 3.3V	GPIO_1 DISP0_DAT9 SD1_DATA3
B-107	WDOG_RST_B_DEB	3.3V	SD1_DATA3

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i.MX53 Features