This section provides an overview of the Opal CPU Module and its capabilities.
It is divided into the following parts:

• Block Diagram
• Freescale i.MX53 Applications Processor
• Memory (RAM and Flash)
• 10/100 Ethernet PHY
• Power Management
• Software Download and Debug

Block Diagram

The block diagram below shows the main components on the Opal CPU Module and how they are connected. The following sections give more details on each component.

Freescale i.MX53 Applications Processor

The Freescale i.MX53 applications processor is central component of the Opal CPU Module. It incorporates a Cortex-A8 core running at 800MHz - 1.2GHz, along with memory controllers and peripherals which enable connections to a wide range of devices.
Read the Freescale i.MX53 Features chapter for more details.

Memory

The Opal CPU Module includes:

• 512Mbytes or 1Gbyte DDR3 memory.
• 512Mbytes - 2Gbytes NAND Flash (optional)

If NAND flash is not fitted, Opal can boot from an SD Card on the base-board.

10/100 Ethernet

The i.MX53 includes a 10/100 Ethernet MAC, and the Opal module expands on this functionality by adding a Micrel KSZ8051 PHY. For detailed information on the MAC, refer to the Freescale documentation.
The signals present on the Opal interface are:

Power Management

Opal includes a Dialog Semiconductor DA9053 Power Management IC. This provides power supplies for the i.MX53 and a number of extra features including battery management, touchscreen and analog inputs. Section 3 has more details on this part.

Debug

Programming and debugging software on the Opal CPU module can be done in a number of ways depending on tools available. These include:

• JTAG. Standard JTAG signals available are TMS, TCK, TDI, TDO and TRST. This requires a JTAG debugger or programmer and appropriate software.
• USB and serial boot mode.
• Ethernet