This page outlines the Freescale i.MX25 features available as part of the Topaz CPU Module. It includes features that are available via external pins on the Topaz, and does not detail internal functions such as memory controllers, internal timers etc. Please note also that not all features listed may be supported by your chosen operating system.
Each section includes:

• A brief overview of the feature along with any specific Topaz implementation notes.
• List of features available on this interface.
• List of external signals used with the interface. These signals are likely to be multiplexed with other signals. The following chapter details each external signal on the Topaz CPU Module along with the i.MX25 functions available on each pad.

For a full description of capabilities and details of registers, please refer to the Freescale i.MX25 Reference Manual.

LCD Controller

Overview

The i.MX5 LCD controller supports a wide variety of panels with resolutions up to 800x600, and the Topaz Module includes all the signals to support these panels.
In addition to standard panels, the i.MX25 also includes a Smart LCD Controller. This controller communicates with panels that have on-board memory.

Features

• Maximum screen resolution of 800x600
• Support for single-screen (non-split) monochrome or color LCD panels, and for self-refresh type LCD panels
• For 4- and 8-bpp color, a palette table is used for remapping of data from memory, independent of the type of panel used. For 1, 2, 12, 16, 18, and 24 bpp, the palette table is bypassed.
• Supports timing requirements for Sharp 240 × 320 HR-TFT panel
• Hardware-generated cursor with blink, color, and size programmability
• Logical operation between color hardware cursor and background
• Hardware panning (soft horizontal scrolling)
• 8-bit pulse width modulator for software contrast control
• Graphic window support for viewfinder function in color display
• Graphic window color keying for graphical hardware cursor
• 256 transparency levels for alpha blending between graphic window and background plane

Signals

The following signals are used by the standard LCD controller.

The following signals are used by the Smart LCD controller (SLCD)

Touch Screen Controller (TSC) and Analog-to-Digital Converter (ADC)

Overview

The i.MX25 includes an on-board controller for 4- or 5-wire resistive touch screens, along with 3 additional general-purpose ADC channels. The touch screen inputs may be used as general-purpose inputs if the touch screen controller is not used.
4-wire touch screens are most common; however, 5-wire screens are more robust and support larger displays (up to 22").

Features

• Integrated 12-bit, 125-kHz ADC
• Supports ratiometric measurement drivers
• Configurable in single-ended or differential (ratiometric) topologies
• Configurable to built-in voltage reference generator or external reference voltage
• Supports 4- and 5-wire touch screens with 5 input channels for touch screen measurements (x+, x-, y+, y-, w)
• Supports general-purpose analog measurements (such as temperature and voltage) with 3 input channels (aux0, aux1, aux2), or 8 input channels if touch interface is not used
• Two independent measurement queues: TCQ for touch screen and GCQ for general-purpose measurements
• Two independent FIFOs, each with 16 entries×16 bits, for storing TCQ and GCQ conversion results
• Supports pen touch screen detection interrupt to awaken the system from sleep mode
• Supports 3 power modes: always-off, power-saving, always-on
• Configurable pen down de-bounce logic
• Configurable LCD noise-reduction logic
• Configurable settling time before each measurement
• Configurable multisampling for each measurement
• Configurable data discarding for each measurement

Signals

USB OTG and Host

Overview

The i.MX25 includes two USB ports, and two on-board PHYs. One port provides On-The-Go (OTG) functionality and can be configured as a host or function port. The second port is a host-only port.
The Topaz CPU makes use of the on-board PHYs to maximize the number of pins available for other functions. While both ports are capable of high-speed operation, the PHY on the Host port only supports full-speed operation.

Features

• High-speed / full-speed / low-speed host-only core:
  • HS/FS ULPI-compatible interface
  • Software-configurable for full-speed / low-speed interface for Serial transceiver
  • Full-speed transceiverless link logic (FS-TLL) for on-board connection to an FS/LS USB peripheral
  • Software-configurable interface for internal serial PHY, external serial PHY and ULPI PHY selection
• High-speed / full-speed / low-speed OTG core
  • HS/FS ULPI-compatible interface
  • Software-configurable for ULPI or serial transceiver interface
  • High-speed (with ULPI transceiver), full-speed and low-speed operation in host mode
  • High-speed (with ULPI transceiver), and full-speed operation in peripheral mode
  • Hardware support for OTG signaling, session request protocol and host negotiation protocol
  • Up to 8 bidirectional endpoints
  • Software-configurable interface for internal UTMI PHY, external serial PHY and external ULPI PHY selection
• Low power mode with local and remote wake-up capability
• Serial PHY interfaces configurable for bidirectional/unidirectional and differential/single ended operation
• Embedded DMA controller

Signals

Enhanced Secured Digital Host Controller (eSDHC)

Overview

The i.MX25 includes 2 eSDHC interfaces which support a wide range of MMC, SD and SDIO devices. The Topaz CPU Module provides access to all pins; however, the second port and data bits 4-7 on port 1 are multiplexed with other commonly used functions.

Features

• Designed to work with MMC, MMC plus, MMC RS, SD memory, miniSD memory, SDIO, miniSDIO, SD Combo, and CE-ATA cards. Compatible with the following specifications:
  • MMC System Specification Version 4.2
  • SD Host Controller Standard Specification Version 2.0, including test event register support
  • SD Memory Card Specification Version 2.0: supports High-Capacity SD Memory Cards
  • SDIO Card Specification Version 2.0
  • CE-ATA Card Specification Version 1.0
• Supports 1-, 4-, or 8-bit MMC modes, 1- or 4-bit SD and SDIO modes, and 1-, 4-, or 8-bit CE-ATA devices
  • Card bus clock frequency up to 52 MHz
  • Up to 416 Mbps of data transfer for MMC cards in 8-bit mode
  • Up to 200 Mbps of data transfer for SD/SDIO cards in 4-bit mode
  • Allows cards to interrupt the host in 1-bit and 4-bit SDIO modes, as well as supporting an interrupt period
• Supports single-block and multi-block read and write
  • Block sizes of 1–4096 bytes
  • Supports pause during the data transfer at block gap
  • Supports Auto CMD12 for multi-block transfer
• Supports read/write features:
  • Write protection switch for write operations
  • SDIO read wait and suspend/resume operations
  • Includes a fully configurable 128x32-bit FIFO for read/write data
• Supports internal and external DMA capabilities
• Supports both synchronous and asynchronous abort
• Host can initiate non-data transfer command while data transfer is in progress
• Support voltage selection by configuring vendor-specific register bit

Signals

General Purpose Input/Output (GPIO)

Overview

The i.MX25 provides 4 GPIO Modules, each with 32 bits.

Features

• General purpose input/output logic capabilities:
  • Drives specific data to output using the data register (DR)
  • Controls the direction of the signal using the GPIO direction register (GDR)
  • Enables the core to sample the status of the corresponding inputs by reading the pad sample register (PSR)
• GPIO interrupt capabilities:
  • Supports up to 32 interrupts
  • Identifies interrupt edges
  • Generates 3 active-high interrupts to the SoC interrupt controller

Signals

GPIO signals are identified in a column in section 4.1.

Universal Asynchronous Receiver/Transmitter (UART)

Overview

The Topaz Module provides access to the 5 UARTS present on the i.MX25. UART1 and UART2 include all "9-wire" signals, while UART3, 4 and 5 include only Tx, Rx, RTS and CTS signals. The Rx, Tx, RTS and CTS signals of UART1 and UART2 are considered primary functions of those pins. The remaining pins for these ports and the other UARTs are multiplexed with other signals on the i.MX25.

Features

• High-speed TIA/EIA-232-F compatible
• 7 or 8 data bits
• 1 or 2 stop bits
• Programmable parity (even, odd, and no parity)
• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
• Edge-selectable RTS and edge-detect interrupts
• Status flags for various flow control and FIFO states
• Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s)
• Voting logic for improved noise immunity (16x oversampling)
• Transmitter FIFO empty interrupt suppression
• UART internal clocks enable/disable
• Auto baud rate detection (up to 115.2 Kbit/s)
• Receiver and transmitter enable/disable for power saving
• DCE/DTE capability
• RTS, IrDA asynchronous wake (AIRINT), receive asynchronous wake (AWAKE), RI (DTE only), DCD (DTE only), DTR (DCE only) and DSR (DTE only) interrupts wake the processor from STOP mode
• Maskable interrupts
• Two DMA Requests (TxFIFO DMA Request and RxFIFO DMA Request)
• Escape character sequence detection
• Software reset (SRST)
• Two independent, 32-entry FIFOs for transmit and receive
• The peripheral clock can be totally asynchronous with the module clock. The module clock determines baud rate. This allows frequency scaling on peripheral clock (such as during DVFS mode) while remaining the module clock frequency and baud rate.

Signals

Inter IC Module (I2C)

Overview

The i.MX25 has three I2C ports. Port 1 is used on the Topaz Module to control the Power Management IC (PMIC), but is available for connection to external devices. Ports 2 and 3 are multiplexed with other functions.

Features

• Compatibility with I2C bus standard
• Multiple-master operation
• Software-programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection

Signals

Configurable Serial Peripheral Interface (CSPI)

Overview

The i.MX25 has 3 CSPI ports. Each SPI port supports up to 4 devices with independent chip select signals.
The Topaz Module brings out port1 as a primary port together with 2 Chip-Select signals. The other ports and Chip Selects are available but are multiplexed with other functions.

Features

• Full-duplex synchronous serial interface
• Master/Slave configurable
• Four chip select (SS) signals to support multiple peripherals
• Transfer continuation function allows unlimited length data transfers
• 32-bit wide by 8-entry FIFO for both transmitting and receiving data
• Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
• Direct Memory Access (DMA) support
• Max operation frequency up to one-quarter of the reference clock frequency.

Signals

Controller Area Network (FlexCAN)

Overview

The i.MX25 includes 2 FlexCAN Modules which are both available on the Topaz Module.

Features

• Full implementation of the CAN protocol specification, version 2.0B
  • Standard data and remote frames
  • Extended data and remote frames
  • Zero to eight bytes data length
  • Programmable bit rate up to 1 Mbyte/sec
  • Content-related addressing
• Flexible message buffers of zero to eight bytes data length
• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
• Individual Rx mask registers per message buffer
• Includes 1056 bytes of RAM used for message buffer storage (64 message buffers)
• Includes 256 bytes of RAM used for individual Rx mask registers (64 mask registers, one for each message buffer)
• Full-featured Rx FIFO with storage capacity for 6 frames and internal pointer handling
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16 standard, or 32 partial (8-bit) IDs, with individual masking capability
• Selectable backwards compatibility with previous FlexCAN version
• Selectable clock source to the CAN protocol interface (bus clock or crystal oscillator)
• Unused message buffer and Rx mask register space can be used as general-purpose RAM space
• Listen-only mode capability
• Programmable loopback mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency due to an arbitration scheme for high-priority messages
• Low-power modes, with programmable wake-up on bus activity

Signals

Synchronous Serial Interface (SSI) and audio Multiplexer (AUDMUX)

Overview

The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices. These serial devices can be standard CODer-DECoder (CODECs), Digital Signal Processors (DSPs), microprocessors, peripherals, and popular industry audio CODECs that implement the inter-IC sound bus standard (I2S) and Intel AC97 standard.
The Digital Audio Mux (AUDMUX) provides a programmable interconnect device for voice, audio, and synchronous data routing between host serial interfaces (such as SSI) and peripheral serial interfaces (that is, audio and voice CODECs, also known as coder-decoders). The AUDMUX interconnections allow multiple, simultaneous, audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations.
Topaz includes all signals (except 1) for AUDMUX ports 3-7. All ports are on 3.3V signals except for port 4 which is available at 1.8V. The signals on port 4 are sufficient to interface to a 1.8V I2S audio codec.

Features

• Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode.
• Normal mode operation using frame sync
• Network mode operation allowing multiple devices to share the port with as many as thirty-two time slots
• Gated Clock mode operation requiring no frame sync
• 2 sets of Transmit and Receive FIFOs. Each of the four FIFOs is 15x32 bits. The two sets of Tx/Rx FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception
• Programmable data interface modes such like I2S, LSB, MSB aligned
• Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
• Program options for frame sync and clock generation
• Programmable I2S modes (Master, Slave or Normal). Oversampling clock, ccm_ssi_clk available as output from SRCK in I2S Master mode
• AC97 support
• Completely separate clock and frame sync selections for the receive and transmit sections. In AC97 standard, the clock is taken from an external source and frame sync is generated internally.
• External ccm_ssi_clk input for use in I2S Master mode. Programmable oversampling clock (ccm_ssi_clk) of the sampling frequency available as output in master mode at SRCK, when operated in sync mode.
• Programmable internal clock divider
• Time Slot Mask Registers for reduced CPU overhead (for Tx and Rx both)
• SSI power-down feature
• Programmable wait states for CPU accesses
• IP Interface for register accesses, compatible with SRS 3.0.2 standard

AUDMUX Signals

CMOS Sensor Interface (CSI)

Overview

The CMOS sensor interface enables connection to external CMOS image sensors. 8-bit, 10-bit and 16-bit sensors are supported. All signals are available on the Topaz Module interface.

Features

• Configurable interface logic to support most commonly available CMOS sensors
• Support for CCIR656 video interface as well as traditional sensor interface
• 8-bit data port for YCC, YUV, or RGB data input
• 8-bit/10-bit/16-bit data port for Bayer data input
• Full control of 8-bit/pixel, 10-bit/pixel or 16-bit/pixel data format to 32-bit receive FIFO packing
• 128 × 32 FIFO to store received image pixel data
• Receive FIFO overrun protection mechanism
• Embedded DMA controllers to transfer data from receive FIFO or statistic FIFO through AHB bus
• Support 2D DMA transfer from the receive FIFO to the frame buffers in the external memory
• Support double buffering two frames in the external memory
• Single interrupt source to interrupt controller from maskable interrupt sources: Start of Frame, End of Frame, Change of Field, FIFO full, FIFO overrun, DMA transfer done, CCIR error and AHB bus response error
• Configurable master clock frequency output to sensor
• Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the camera (only for Bayer data and 8-bit/pixel format)

Signals

Keypad Port (KPP)

Overview

The Keypad port supports a matrix keypad up to 8x8.

Features

• Supports up to an 8 x 8 external key pad matrix
• Port pins can be used as general purpose I/O
• Open drain design
• Glitch suppression circuit design
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Synchronizer chain clear
• Supports a two-point and three-point contact key matrix

Signals

General Purpose Timer (GPT)

Overview

The i.MX25 has 4 General Purpose Timers (GPT). These have compare and capture inputs that are available on the Topaz Module interface.

Features

• One 32-bit upcounter with clock source selection, including external clock
• Two input capture channels with programmable trigger edge.
• Three output compare channels with programmable output mode. Forced compare feature also available
• Can be programmed to be active in low-power mode
• Interrupt generation at capture, compare, rollover events
• Free-running or restart modes for counter operation

Signals

 Enhanced Periodic Interrupt Timer (EPIT)

Overview

The enhanced periodic interrupt timer (EPIT) is a 32-bit set-and-forget timer that begins counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. There are X of these modules on the i.MX25 and they include an output signal which is available on the Topaz Module.

Features

• 32-bit down counter with clock source selection
• 12-bit prescaler for division of input clock frequency
• Counter value can be programmed on the fly
• Can be programmed to be active during low-power modes
• Interrupt generation when counter reaches the Compare value

Signals

Pulse-Width Modulator (PWM)

Overview

The i.MX25 includes 4 Pulse-Width Modulator channels. These have a 16-bit resolution and include a FIFO to generate sound.

Features

• 16-bit up-counter with clock source selection
• 4×16 FIFO to minimize interrupt overhead
• 12-bit prescaler for division of clock
• Sound and melody generation
• Active high or active low configured output
• Can be programmed to be active in low-power and debug modes
• Interrupts at compare and rollover

Signals

1-Wire Interface

Overview

The 1-Wire Module provides access to devices that comply with the Maxim-Dallas define protocol.

Features

• Performs the 1-Wire bus protocol to communicate with an external 1-Wire device
• Provides a clock divider to generate a 1-Wire bus reference clock (derived from the main clock provided internally to the module)
• Supports byte transfers with optional interrupts for more efficient programming
• Provides search ROM accelerator mode to speed the search ROM protocol

Signals

Watchdog (WDOG)

Overview

The i.MX25 includes watchdog functionality as a method of escaping from unexpected events or programming errors.

Features

• A configurable time-out counter with time-out periods from 0.5 seconds up to 128 seconds and after time-out expiration results in assertion of the wdog_rst reset signal
• Time resolution of 0.5 seconds
• A configurable time-out counter that can be programmed to run or stop during low-power modes
• A configurable time-out counter that can be programmed to run or stop during DEBUG mode
• Programmable interrupt generation prior to time-out
• The time duration between interrupt and time-out events can be programmed from 0 to 127.5 seconds in steps of 0.5 seconds
• A power-down counter with a fixed time-out period of 16 seconds which, if not disabled after reset, asserts the WDOG signal low
  • The power-down counter is enabled out of any reset (POR, Warm / Cold reset) by default

Signals

Subscriber Identification Module (SIM)

Overview

The i.MX25 includes 2 Subscriber Identification Modules (SIM). Each SIM is designed to facilitate communication to SIM cards or Eurochip pre-paid phone cards. The SIM Module has two ports that can be used to interface with the various cards. The interface with the core is a 32-bit connection as described in the reference document IP Bus Specification.

Signals